The present invention relates to the positioning of a data strobe within a data valid window in a processor-based system that executes data read and write operations by accessing memory modules such as DIMMs (double in-line memory modules). In particular, the system and method described herein are adapted to accommodate the stringent requirements presented by DDR (double-data read) systems, which clock memory data at both the positive and negative edges of a data strobe (referred to as DQS) signal, and which are becoming more common in high-end computer systems.
DDR devices use a source-synchronous clocking mechanism (the DQS strobe) to transfer data between the DDR device and the memory controller. During a read access, the DDR device provides read data substantially aligned with the DQS data strobe, and the memory controller, such as a DDR SDRAM controller, delays the DQS data strobe by an amount determined to accommodate the appropriate setup and hold delays for the accessed device, thus allowing the requested data to be correctly captured. In a write operation, the memory controller coordinates the data storage so that it occurs within the data valid window.
A read operation is illustrated in FIG. 1, where line 1A shows the timing of a data stream 100, a DQS data strobe 102 for the data stream 110, and the DQS strobe 104 after a predetermined delay. Each data period 110, 120, 130, 140 . . . (corresponding to requested data bytes) of the data stream 100 has an initial transition period (111, 121, etc.); a setup period (112, 122, etc.); a hold period (114, 124, etc.); and a tail transition period (115, 125, etc.).
Generally, the “setup” time or period for a given device is the time required for that device to stabilize after receiving a command, data or other signal. In the case of a read request, typically there will be a read-data FIFO queue, and the setup time is the time needed by that FIFO (in particular, one or more flip-flops within that FIFO) to stabilize the data. The “hold” time or period is the time that the device (or the FIFO) is designed to keep the requested data available before the next data cycle.
For example, in the case of a read-data request for a DDR device, the relevant JEDEC standard (the Double Data Rate (DDR) SDRAM Specification JESD79—June 2000, which is incorporated herein by reference) specifies the setup and hold period durations for 133 MHz and 100 MHz system clocks. For example, it is appropriate if a setup and hold period in the aggregate amount to at least 35% of the data capture period. Thus, if the system runs at 100 MHz, the data capture period is 10 ns, so the setup/hold period is 3.5 ns. There are two such 3.5 ns periods for each 10 ns period in a DDR system, since data is clocked on both rising and falling edges of the system clock, i.e. in FIG. 1 both on positive edges 150, 170, 190, etc. and on negative edges 160, 180, etc. of the data strobe DQS.
In FIG. 1, region 111 of the data period 110 is the initial transition period following a data read request, during which the data bits are sent by a DIMM or other memory device to the read data FIFO. Region 112 is the setup time for the read data FIFO. For data to be reliably captured, the setup time 112 and hold time 114 should be at least some minimum time specified for the given device, e.g. a flip-flop for the FIFO.
The rising edge 155 of an appropriately delayed DQS strobe should occur no earlier than the minimum setup time required by the device in question, and before the end of the hold period.
FIGS. 2A-2C are timing diagrams illustrating possible arrival times of the DQS data strobe at a requesting device with respect to a data signal 110. FIG. 2A shows the arrival of a rising edge 152 of a DQS strobe during the setup time 112. When this occurs, spurious data can be captured, since the receiving device may not have had time to stabilize. In order to avoid this, in present systems a circuit may be used that delays the issuance of the DQS strobe, so that it arrives at the requesting device after the setup requirement is met for the receiving device, and not so late as to exceed the hold duration.
However, care must be taken that the DQS is not delayed too much, or it might occur at or near the end of the hold period 114, as in FIG. 2B, with the risk of attempting to capture the data during the tail transition time, again leading to erroneous data.
Ideally, the DQS is delayed as in FIG. 2C, so that it is presented to the requesting device after the setup 112 has taken place and before the end of the hold period 114.
Not only does the setup take a certain amount of time, but the bits that make up a data word may take different paths from a memory device (e.g. a DIMM) through the system (even though they are all on the same bus), resulting in misalignment—i.e., different arrival times at the requesting device. Thus, as FIG. 3 illustrates, for an eight-bit byte, some bits (e.g., data bits 0 and 1) may arrive before others (e.g., bits 2, 3 and 7), and it is important that the DQS strobe does not occur before all bits are present, or the captured data will be incorrect.
The above factors can shrink the window in which the DQS can be issued and reliably capture the desired data. Because of the bits arriving at different times, the reliable data capture window may be reduced by 80-90%, in the present example resulting in, perhaps, a 400-500 ns window.
Current systems may use phase-locked loops (PLLs) or other mechanisms to compensate for circuit timing variations caused by PVT (process-voltage-temperature) differences. Such mechanisms will keep the system clock's frequency within the capture and tracking ranges of the PLL, but this does not solve the problem of timing a DQS strobe as discussed above.
A PLL is inappropriate to time a DQS strobe, in part because a PLL requires a constant clock signal (unlike a DQS strobe, which can stop between data transfers); and additionally, because a PLL is designed to minimize variations in signal frequencies (and hence timing differences), whereas a DQS strobe must be affirmatively delayed for correct timing with the data signals.
A delay line may be used for this purpose, i.e. to compensate for PVT in timing the DQS to track the setup and hold time periods. E.g., if the entire data signal 110 (including transition, setup and hold periods) takes 5 ns, then a fixed delay of about 2½ ns would place the DQS near the center of the 3½ ns window 116. This would delay the DQS rising edge 155 (see FIG. 1) for the appropriate time. If the initial transition time is no more than ½ ns, then the fixed 2½ ns delay would put the rising edge 155 at the 3-ns point in the 5-ns window 116, and within the 3½ ns setup/hold period (112 plus 114).
A problem with attempting to specify a fixed delay period is that as the chip or circuit warms up under load, the delay period will lengthen, while the data window remains within tight parameters, while the “fixed” delay period typically may vary to a greater degree. In this case, a situation as illustrated in FIG. 2B can occur. Compensation for heating by reducing the delay time can pull the DQS strobe back too far, as in FIG. 2A, when the load on the circuit load is reduced. Although tight circuit board specifications can alleviate this—e.g. by careful routing and linking the data lines as closely as possible to the clock—the problem of DQS strobe timing persists.
Because of strict DDR timing requirements and faster computer systems in general, a system is needed that reliably increases the rate of data transfer operations while taking PVT variations into account. In particular, such a system is needed that can dynamically compensate for PVT changes, substantially in real time or as desired by a user, and ensure that data strobes are provided to a receiving device during the data valid window.
Once the problem of timing the DDR DIMM strobe with a data valid window is solved, as in the present application, a determination must be made of when to carry out a calibration operation, so that correct timing compensation can be achieved. In particular, the calibration operation must avoid corrupting data transfers, such as a read data capture, and should be carried out frequently enough to track potential or actual changes in propagation times. A system is needed that can accommodate both on-demand and automatically scheduled calibration operations.